Electronic circuit with asynchronously operating components

ABSTRACT

An electronic circuit that comprises components that operate asynchronously of one another. An interface element has inputs coupled to a respective one of the components. The interface element supplies a logic output signal that is a logic function of signals at the inputs and dependent on the relative timing of the signals at the inputs. The electronic circuit is switched to a test mode, in which test input signals are applied to the electronic circuit from a test signal source. During test a difference is caused to occur between the time intervals after which the test signal source affects different ones of the signals at the inputs of the interface element. Preferably the test control circuit activates said difference in the test mode and not in the normal operating mode.

The invention relates to a method of testing an electronic circuit withasynchronously operating components and to an electronic circuit withasynchronously operating components. For various reasons it may bedesirable to include within an electronic circuit different componentsthat operate asynchronously from one another. Asynchronous operationmeans that the electronic circuit lacks an overall clock signal thattriggers all operations of the electronic circuit in a fixed timerelation to one another. Asynchronously operating circuit include forexample circuits that use handshake signals to synchronize pairs ofcommunicating circuits, circuits that use independent clocks fordifferent components and mixtures of such circuits.

Although different components of the electronic circuit generallyoperate asynchronously, some synchronization at isolated points in timeis sometimes necessary, for example to exchange data or to sequence someoperations. For this purpose special interface elements are used thatgenerate logic signals that depend on logic input signals from thecomponents and on the relative timing of transitions in these inputsignals. One example of such an interface element is an arbiter circuit,which generates successive grant signals, each time selecting no morethan one of the components on request from the components on a firstcome first served basis. The logic function of the arbiter is to makeone of its outputs logic high when a logic low to high transition isdetected on a corresponding input and none of the other outputs is logichigh.

Testing of electronic circuits is conventionally performed by applyingdifferent combinations of input signals to the circuit and comparingeach resulting response at the outputs with a predetermined “correct”pattern, either bit for bit or through a signature that is compoundedfrom the response. A preferable technique for applying test patternsuses a so-called scan chain, which switches a number of elements (suchas flip-flops) of the electronic circuit to form a shift register duringtest. This shift register is called the scan chain. The input signalsare transported into the electronic circuit through the scan chain andapplied to logic circuitry from the scan chain. Subsequently theresulting response pattern is loaded from the outputs of the logiccircuitry into the scan chain and transported through the circuit viathe scan chain to a test result comparator. Thus, a thorough test can beexecuted with little overhead.

This test technique does not work satisfactorily for interface elementsbetween asynchronously operating circuits. Due the fact that the logicoutput signals of such interface elements depend on the relative timingof the input signals, simultaneous application of different inputsignals during the conventional test does not lead to reproducibleresults. The relative timing of the signals that arrive at the interfaceelement may depend on the speed of the logic circuitry between the testinput and the logic circuitry. This causes difficulties during testcomparison.

In addition, any changes in the input signals of the interface elementsprior to the application of the test signals may affect the logic valueof the output signals, and even the question whether the output signalshave any defined logic level. A particular problem here ismetastability, which affects the time before the interface elementassumes a well-defined output, dependent on the closeness of the timingof the input signals. When changes occur in the input signal of theinterface element, due to transport of input signals through the scanchain, this may bring the interface element to an undefined state at thestart of application of the test input signals. This also makes theoutput signals unpredictable. Similar problems may arise during samplingof output signals from interface elements during normal operation.

Among others, it is an object of the invention to provide for anelectronic circuit that permits well defined sampling of output signalsfrom an interface element whose logic output depends on the relativetiming of its input signals.

Among others, it is an object of the invention to provide for anelectronic circuit with asynchronously operating components and aninterface element coupled to the components, which provides forwell-defined testing of the interface elements.

Among others, it is an object of the invention to provide for a methodof testing of electronic circuits with asynchronously operatingcomponents which provides for well defined output signals from interfaceelements whose logic output depends on the relative timing of its inputsignals.

Among others, it is a further object of the invention to provide forsuch a method or electronic circuit which provides well defined outputsignals during test even if test input signals affect the interfaceelement through intervening logic circuitry or if varying patterns ofinput signals are applied to the interface element prior to applying arelevant test signal.

Among others, it is a further object of the invention to provide forsuch a method or electronic circuit which does not substantially affectthe speed of the electronic circuit during normal operation, when theelectronic circuit is not being tested.

The invention provides for a circuit according to claim 1. According tothe invention the electronic circuit provides for sampling after inwhich input signals are forced to affect the interface elements withdifferent delays, the delays being activated selectively prior tosampling. Thus, on one hand the delays do not normally slow down thecircuit and on the other hand the delays ensure a well-defined temporalsequence in which the signals affect the interface element. This ensuresa predictable output signal of the interface element when it is sampled.This is used in particular for by a test control circuit that switchesthe electronic circuit between a test mode and a normal operating mode.In the test mode normal input signals are replaced by test signals froma test signal source. The test control circuit activates the differentdelays in the test mode and not in the normal operating mode. Thus, onone hand the delays do not slow down the circuit in the normal operatingmode and on the other hand the delays ensure a well-defined temporalsequence in which the test signals affect the interface element in thetest mode. This ensures a predictable output signal of the interfaceelement when it is tested. As a result the interface element can betested using conventional test circuits that compare the output with astandard “good” output.

In an embodiment, the interface has enabling inputs that are used totemporarily disable the inputs of the interface element duringactivation, and to reenable the inputs delayed with respect to oneanother. Thus, it is ensured in a simple way that the signals atdifferent inputs will affect the interface element in a well-definedtemporal sequence. As an alternative a well-defined temporal sequencemay be realized by using one or more delay lines in the normal signalpaths between the test signal source and the different inputs of theinterface elements, the delays being activated temporarily, for examplein the test mode. However, by using enabling of the inputs of theinterface elements, it is ensured that the interface element cannot bebrought into a meta-stable state by changes in the input signals closelybefore the start of relevant testing. In addition the temporal sequenceof the effect of the signals is independent of any logic signal valuedependent delay in logic circuitry between the test signal source andthe interface element.

In yet a further embodiment the interface element is implemented as aset of cross-coupled logic gates, in which under control of clocksignals the logic gates can be disconnected from the power supply so asto dynamically retain logic data. As described in a co-pending patentapplication of the inventors this can be used to switch the logic gatesinto a configuration in which test data can be transported to or fromthe logic gates though a path that differs from the signal paths duringnormal operation. In the present invention, the clock signals ofdifferent ones of the logic gates are activated so that the powersupplies to different ones of the logic gates switch on with a delaywith respect to one another. This allows signals to affect the interfaceelement in a well-defined temporal sequence.

These and other objects and advantageous aspects of the circuit andmethod according to the invention will be described in more detailsusing the following FIGS.

FIG. 1 shows an electronic circuit;

FIGS. 2-5 shows embodiments of an interface element;

FIG. 6 shows a further electronic circuit;

FIG. 7 shows a clocked NOR gate.

FIG. 1 shows an electronic circuit. The electronic circuit comprisescombinatorial logic circuitry 10, storage elements 12 and a test controlunit 14. Combinatorial logic circuitry 10 has inputs and outputs coupledto storage elements 12 (although single lines are shown to connect thecombinatorial circuitry 10 and other components, it should be understoodthat each of these lines may represent a plurality of independentconnections). Test control unit 14 is coupled to storage elements 12.The electronic circuit is also shown to contain additional combinatoriallogic circuitry 16 a, b, a delay element 17 and an interface element 18.Test control unit 14 has a test preparation output coupled to enablinginputs 19 a,b of interface element 18, directly and via delay element 17respectively.

In operation test control unit is coupled to storage elements 12 in aconventional way to select between a normal mode of operation and a testmode of operation. In the normal mode of operation data from storageelements 12 is fed to combinatorial logic circuitry 10 and the resultinglogic output data of combinatorial logic circuitry 10 is loaded into thestorage elements 12. From there the data may again be fed tocombinatorial logic circuitry 10 and so on. Some of the storage elements12 may even be transparent in normal operation. Also data from storageelements 12 may be fed to external outputs or data may be fed to storageelements 12 from external inputs. In the test mode, test control unitcommands storage elements 12 to operate as a shift register to entertest signal patterns, to supply these signal patterns to combinatoriallogic circuitry 10, to capture the resulting test output patterns and toshift out the test signal patterns for inspection.

In normal operation different ones of the storage elements 12 mayoperate asynchronously from one another. That is, their timing may becontrolled by clock signals that are not synchronized, or they mayoperate using handshake signals instead of clock signals or any otherform of timing may be used that does not ensure a predetermined timingrelationship between different ones of the storage element 12. This typeof asynchronous operation requires special types of interface elements18. These interface elements 18 produce logic output signal levels thatdepend not only on the logic level of its input signals, but also on therelative timing of transitions in the logic levels of its input signals.By way of example only one such interface element 18 is shown, togetherwith separate logic circuitry 16 a,b between the respective inputs ofthis interface element 18 and the storage elements 12. However, it willbe understood that in practice the electronic circuit may contain manysuch interface elements 18. Also the way this interface element iscoupled to storage elements 12 is only shown by way of example. When aplurality of interface elements is present they may share delay element17.

One example of such an interface element is an arbiter circuit, whichhas inputs for receiving request signals, and outputs, eachcorresponding to a respective one of the inputs, for producing grantsignals. The arbiter makes at most one of the grant signals logic highat a time on a first come first served basis. More particularly, if noneof the outputs is logic high the arbiter responds to a low to hightransition of the signal at a first one of its inputs by making thesignal at a corresponding first one of its outputs logic high. Thearbiter makes the signal at the first one of the outputs logic low whenthe signal at the first one of the inputs becomes logic low. If a low tohigh transition occurs at a second one of the inputs when the first oneof the outputs is logic high, the arbiter does not make thecorresponding second one of the outputs logic high until the signal atthe first one of the outputs has been made logic low. Thus, the logicoutput levels depend on the relative timing of transitions of the inputsignals.

The test preparation output of test control unit 14 and delay element 17serve to make interface element 18 produce predictable output signalsduring test. In normal operation test control unit 14 first keeps thetest preparation output to a level that disables the inputs of interfaceelement 18. During a test in test mode, test control unit 14 firstdrives the test preparation output to a level that disables the inputsof interface element 18. While the signal at the test preparation outputis at this level storage elements 12 are controlled to set up a testpattern that affects the signals at the inputs 19 a,b of interfaceelement 18. Subsequently, test control unit changes the level of thesignal at the test preparation output, so that the inputs of interfaceelement 18 are enabled. Due to the operation of delay element 17 a firstone of the inputs 19 a is enabled a predetermined time interval before asecond one of the inputs 19 b is enabled. Thus, the signals from storageelements 12 affect interface element 18 in a well defined temporalsequence, giving rise (if interface element operates properly) to welldefined output signals, which are loaded into storage elements 12 forsubsequent inspection.

Although the invention has been illustrated in FIG. 1 with a testinterface having separate logic circuitry 16 a,b between it and storageelements 12, and outputs coupled directly to storage elements 12, theinvention is of course not limited to such a configuration: interfaceelement 18 may have it inputs coupled directly to storage elements 12and/or its outputs may be coupled to storage elements via further logiccircuitry (not shown). Also, although an interface element 18 is shownwith an output for each input, which is typical for an arbiter, ofcourse interface elements with fewer or more outputs may be used, ofwhich some or all may be coupled to storage elements 12. Furthermore,although the invention has been illustrated in a form where results ofthe test are shifted out of scan chain 12, it will be understood that itis not necessary that all results are inspected explicitly, for examplea signature of the results may be formed in a conventional way.

FIG. 2 shows an example of an interface element 18 in combination with adelay element 17. Interface element 18 contains a flip-flop circuit 20,an output stage 22 and enabling gates 24, 26. The flip-flop circuit 20contains a pair of cross-coupled NAND gates 200, 202. The output stagecontains a pair of inverters 220, 222, each coupled between the outputof a respective one of the NAND gates 200, 202 of flip-flop 20 and arespective one of the outputs of interface element 18. Preferably,inverters 220, 222 have been designed so that their threshold voltage islower than that of NAND gates 200, 202. Enabling gates 24, 26 are ANDgates, each having a first input coupled to the signal inputs of theinterface element 18, a second input coupled to a respective one of theinputs 19 a,b of interface element 18, and an output coupled to an inputof a respective one of the NAND gates 200, 202 in flip-flop 20. Thus,second inputs of AND gates 24, 26 are respectively coupled directly andcoupled via delay element 17 to the test preparation output of the testcontrol unit 14 as shown in FIG. 1. In operation, interface element 18will produce logic low output signals when both its input signals arelogic low. In this case, NAND gates 200, 202 produce logic high outputsignals that are inverted by inverters 220, 222. In normal operation thetest preparation signal at the second inputs of AND gates 24, 26 islogic high. When one of the input signals is made logic high the NANDgate 200, 202 that receives this input signal via AND gates 24, 26switches its output to logic low, resulting in a logic high at theoutput of the corresponding inverter 220, 222. If the other one of theinput signals later also switches to logic high, flip-flop 20 simplyretains its earlier state.

When both input signals switch high nearly simultaneously inverters 220,22 do not produce a logic high output signal until the output signalfrom NAND gates 200, 202 has dropped below the threshold level ofinverters 220, 222. Because the threshold level of NAND gates 200, 202is higher than that of inverters 220, 222, this will only happen onceflip-flop 20 starts to assume a definite state. Dependent on thetemporal closeness of transitions at the inputs, it may take some timebefore flip-flop 20 starts to assume this definite state.

Of course, it will be appreciated that the details of the interfaceelement are not relevant to the invention, for example, instead of usinginverters 220, 222 with special thresholds, a special semi-inverter maybe used with a series arrangement of the main current channels of aP-MOS transistor and an NMOS transistor, one of the outputs of theflip-flop 20 being coupled to the control electrodes of thesetransistors, the series arrangement being coupled between the otheroutput of flip-flop 20 and a power supply connection, an output signalbeing derive from a node between the main current channels. In thissemi-inverter circuit the output can only make a transition when thedifference between the output levels of the signals at the outputs offlip-flop 20 exceeds the threshold level of one of the transistors inthe semi-inverter. When the test preparation signal is low in the testmode, AND gates 24, 26 disable the signals from inputs 19 a,b. Thesignals at the inputs of NAND gates 200, 202 in flip-flop 20 are bothlow, forcing the output signals of flip-flop 20 to logic high and theoutput signals of inverters 220, 222 to logic high. Still in the testmode test control unit 14 subsequently makes the test preparation signallogic high, causing first a first one of AND gates 24 to pass the signalfrom input 19 a and after a delay determined by delay element 17,causing a second one of the AND gates 26 to pass the signal from input19 b. Thus, the signals from inputs 19 a,b reach flip-flop 20 in a welldefined temporal sequence, leading to a well-defined state of flip-flop20 in a well defined time. As a result, the output signals frominterface element during this test are predictable, so that they may becompared with a standard “correct” output value. Any kind of delayelement 17 may be used. Since the delay caused by delay element 17 isonly determinative for the test when the test preparation signal enablesthe inputs of interface element 18 an asymmetric delay element may beused, which provides a different delay, or no delay, when the inputs ofinterface element 18 are disabled. Using a reduced delay on disablingmay be used to speed up the test. Although only one delay element isshown, it will be understood that delay elements may be included betweentest control unit 14 and both of the inputs 19 a,b, as long as thedelays caused by the delay elements provide the required differencebetween the delays with which the inputs are enabled.

FIG. 3 shows an alternative example of an embodiment of interfaceelement. In this embodiment delay element 17 has been omitted and adelay element 30 has been included between AND gate 36 and the input ofNAND gate 202. Thus, it is ensured that there is a delay of the effectof making the test preparation signal high. This circuit has thedisadvantage that the delay always affects the input signals, alsoduring normal operation. However, in some circuits this is not aproblem. Similarly, as an alternative to using disabling inputs, one ormore delay elements may be inserted anywhere in one or more signal pathsform storage elements 12 to interface element 18, so as to ensure a welldefined temporal sequence of input signals when a test pattern is newlyapplied from storage elements 12. In this case test control unit 14 ispreferably coupled to these delay elements so as to relatively reducetheir delay during normal operation and to relatively increase theirdelay in the test mode. Thus, no unnecessary delay occurs during normaloperation. Preferably, in this case, storage elements 12 are designed sothat they retain a fixed output signal during the time when the testpattern is shifted into the storage elements.

Of course, many other circuits may be used to realize an appropriateinterface element. For example, AND gates 24, 26 may be eliminated byusing three-input NAND gates in flip-flop 20 and coupling the testpreparation signal to the third inputs. Different kinds of flip-flopsmay be used, using for example cross-coupled NOR gates, the definitionof one or more of the logic levels in the circuit may be inverted,etcetera. What matters is that the normal input signals of the interfaceelement are temporarily disabled from influencing the state of theinterface element prior to test, and are subsequently reenabled duringtest in a way that leads to an unambiguously predictable temporalevolution of the input signals of the interface element.

Also, the invention is not limited to arbiter functions or mutualexclusion functions as shown in FIG. 2. Any kind of known interfacefunction may be used that depends on relative timing of its inputsignal. Enabling circuits may be added to known interface circuits, forexample by adding AND gates such as AND gates 24, 26 at their inputs, orby modifying these circuits in any other appropriate way. By driving theenabling inputs from test control unit 14 with different delays, awell-defined response is obtained.

In particular the invention is of course not limited to two-inputinterface elements. Interface elements with more than two inputs caneasily be realized by combining a number of two input interfaceelements. In this case the enabling signals should of course enabledifferent inputs with different delays. When interface elements are usedin cascade, successive interface elements may be enabled each time witha greater delay than their predecessors in the cascade. Of course,instead of combinations of two-input interface elements, any multi-inputinterface circuit may be used, with added enabling inputs, which enableinput signals from different inputs with different delays.

FIG. 3 illustrates a circuit in which the interface circuit, whendisabled, returns its outputs to a state with a zero logic level at bothoutputs, and, when enabled, responds to the input signals starting fromthat state. Of course, the invention is not limited to such a startingstate. Without deviating from the invention, interface elements may beused that set the outputs to different states.

FIGS. 4-5 show examples of interface element that assume differentstates when disabled. FIG. 4 shows an interface element 18 that goes toa state with both inputs high when disabled. FIG. 5 shows an interfaceelement 18 that goes to a state with one input logic high and anotherinput logic low when disabled. In a further embodiment, the interfaceelement may be designed so as to assume a programmed initial state, thatis selected under control of a test control signal supplied during test,for example from storage elements 12. Thus, operation of the interfaceelement may be tested under different conditions of relative timing.

The invention is not limited to interface elements that are used asmutual exclusion elements, such as described in the preceding. Theinvention can be applied to any type of interface element that producesa timing dependent output signal. For example, the invention could beapplied to a set-reset flip-flop. Such a flip-flop is set to a firststate by a pulse on a first signal line and reset to a second state by asignal on a second signal line. The last pulse to end determines thesubsequent state of the set-reset flip-flop. During normal operation theset and reset pulses do not overlap, but in the test mode there is arisk of such overlapping pulses, when the circuit is prepared for a testor when a test pattern is applied that cannot occur during normaloperation. This may lead to undeterministic behavior during the test.

Cross-coupled NAND gates, such as those of FIG. 2 form an example of acircuit that can be used as a set-reset flip-flop, when a pulse thattemporarily drops to logic low is used at the inputs of the NAND gates.By temporarily disabling the input signals from influencing the state ofthe circuit prior to the test, and reenabling the input signals to do soduring the test, a well-defined test is realized.

FIG. 6 shows part of an electronic circuit according to an embodiment ofthe invention. The electronic circuit contains various combinatoriallogic circuits 60 a-c, a scan chain 62, a test control unit 64, a delaycircuit 66 and an interface element 68. Interface element 68 is part ofscan chain 62. Test control unit 64 is coupled to scan chain 62 and thecombinatorial logic circuits have inputs and outputs coupled to scanchain 62. Scan chain 62 contains sections 620 a,b, interface element 68being coupled between a pair of sections 620 a,b via scan paths.Interface element 68 is also coupled to sections 620 a,b via signalinputs and outputs of sections 620 a,b and combinatorial logic circuits600 a,b via signal paths. By way of example an additional combinatoriallogic circuit 60 c has been shown. It will be understood that any numberof such combinatorial logic circuits 60 c may be present and that thecombinatorial logic circuits 60 a-c may be coupled anywhere to scanchain 62.

By way of examples an interface element that operates as a set-resetflip-flop is used. Interface element 68 contains a pair of cross-coupledNOR gates 680 a,b, a pair of output inverters 682 a,b and a pair ofscanning inverters 684 a,b. Nodes 686 a,b each are coupled to an outputof one of the cross-coupled NOR gates 680 a,b, an output of one thescanning inverters 682 a,b and an input of one of the output inverters684 a,b. NOR gates 680 a,b, scanning inverters 682 a,b and outputinverters 684 a,b are clocked devices, with clock inputs coupled toclock outputs of test control unit 64. The clock inputs of NOR gates 680a,b are coupled to the same clock output of test control unit 64, theclock input of a first one of NOR gates 680 a directly, and the clockinput of a second one of NOR gates 680 b via delay circuit 66. Interfaceelement 680 is coupled to the scan path via scanning inverters 682 a,band to the signal paths via output inverters 684 a,b.

FIG. 7 shows an example of a clocked NOR gate 680 a of the type used ininterface element 68. The clocked NOR gate 680 a contains a logicsection 70, and power supply transistors 76 a,b. Logic section 70contains PMOS transistors 72 a,b and NMOS transistors 74 a,b coupledbetween local power supply nodes 75 a,b so as to perform a NOR function,with an output at an output node 79. Power supply transistors 76 a,bhave main current channels coupled between local supply nodes 75 a,b andcommon supply nodes 78 a,b that supply power to a larger part of theelectronic circuit. The clock inputs of NOR gate 680 a are coupled tocontrol electrodes of power supply transistors 76 a,b. The signal inputsand outputs of NOR gate 680 a are coupled to the control gates of PMOStransistors 72 a,b and NMOS transistors 74 a,b and to output node 79respectively. Scanning inverters 682 a,b and output inverters 684 a,bhave a similar structure, except of course that logic section 70 isreplaced by a logic section that is appropriate to their function. Thefunction of power supply transistors 76 a,b is to control interruptionof the connections between both common power supply nodes 78 a,b andoutput node 79. It will be understood that this function could beachieved by placing either or both of these transistors at otherpositions in the clocked NOR gate, for example between the transistorsof logic section 70 and output node 79.

In operation the circuit of FIG. 6 is capable of operating in a normalmode and in a test mode. In the normal mode the clock signals from testcontrol unit 64 make NOR gates 680 a,b operate as normal NOR gates, bymaking the main current channels of power supply transistors 66 a,bconductive. In the normal mode the clock signals similarly make outputinverters 684 a,b operational, but scanning inverters 682 a,b aredisabled. In the normal mode the sections 620 a,b of scan chain 62function as intermediate storage elements for signals that travelthrough combinatorial logic circuits 60 a-d. Interface element 68operates as a set reset flip-flop. By applying pulses that temporarilygo high at the normal inputs the interface element can be set and reset.

In the test mode, the circuit first enters a shift-in phase in whichtest patterns are shifted through scan chain 62. During shiftinginterface element 68 operates as a dynamic shift register in scan chain.In this mode the scan chain 62 runs successively through one of thescanning inverters 682 a,b and the corresponding output inverter 684a,b, subsequently it runs though the other scanning inverter 682 a,b andthe corresponding output inverter 684 a,b. Test control unit 64 realizesshifting by supplying a clock signal that removes the power supply fromNOR gates 680 a,b, and by applying clock signals to scanning inverters682 a,b and output inverters 684 a,b. that alternate allow power supplycurrent to flow to scanning inverters 682 a,b and to output inverters684 a,b in alternating phases. Thus, information from the input of ascanning inverter 682 a,b is transferred inverted to the output of thescanning inverter 682 a,b in one phase, and in another phase theinformation is transferred inverted from the output of the scanninginverter 682 a,b to the output of the output inverter 684 a,b, in thesecond phase new information is also transported to the input of thescanning inverter 682 a,b. With a series of such alternating phases atest patterns is transported through scan chain 62.

Once the test pattern has arrived at the relevant storage elements, anevaluation phase starts. Test control unit 64 clocks scanning inverters682 so that they receive no power supply current, and it clocks outputinverters 684 a,b so that they do receive power supply current. Testcontrol unit 64 then clocks NOR gates 680 a,b so that they receivedpower supply current. Because of delay element 66 one of NOR gates 680a,b starts receiving power supply current a well define time intervalbefore the other. Once a NOR gate 680 a,b starts receiving power supplycurrent it starts passing signals from its inputs, including therelevant input signal of interface element 68, to its output.

Thus, the input signal can start affecting the state of the interfaceelement one after the other. As long as the input signals do not affectthe state (being logic low for example) the state is determined by datafrom the test pattern that has been fed to the interface element throughscan chain 62 during the shift phase. At the end of the evaluation phasesignals from scan chain 62 have resulted into output signals at theoutputs of combinatorial logic circuits 60 a-d and interface element 68.

After the evaluation phase output data is captured by scan chain 62 andshifted out through scan chain 62 in a shift-out phase. Shift out iscontrolled by test control unit 64 in basically the same way as shiftin.

Thus, the circuit of FIG. 6 provides for both enabling of the inputsignals and setting of the initial state of interface element 68, with acircuit that requires a small amount of components. Although the circuitis illustrated in terms of a set-reset flip-flop it will be readilyappreciated that a similar circuit can be realized with an interfaceelement that functions as a mutual exclusion element. Also cross-coupledNAND gates may be used instead of NOR gates 680 a,b.

Moreover, it will be appreciated that the invention is not limited tothe circuit of FIG. 6, for example the output of one output inverter 684a,b need not be directly coupled to the scanning inverter 682 a,b of theinterface element 68. Other storage elements may intervene. In fact itmay not be necessary that both NOR gates 680 a,b are included in scanchain 62: one of the NOR gates may be controlled as shown in FIG. 1.Similarly, it is not necessary to use output inverters 684 a,b as partof the scan chain: other inverters may be used. Also, scan chain 62 neednot be used for both shifting test patterns in and results out, othermethods might be used to apply test patterns or read result patterns.

Although the circuit has been described in terms of testing, it will beappreciated that an interface element with an activatable differencebetween the delays with which input signals affect the interface circuitcan also be used outside a test context, for example for samplingpurposes. For example, to poll interrupt requests it may be necessary tosample the output of a mutual exclusion element. Such sampling may leadto errors if a meta-stable state of the interface element occurs at thetime of sampling. By creating a differential delay, and more preferablyby disabling the inputs of the interface element temporarily andreenabling them with a delay relative to one another prior to samplingsuch meta-stable states can be prevented, or at least the probability oftheir occurrence can be reduced. However, it is especially advantageousto control activation of the delay with a test control circuit, becausetest procedures require some abnormal operation of the circuit (such astransport of test patterns) that would distort the test results thatinvolve interface elements unless the test control is capable ofensuring a deterministic response.

1. An electronic circuit comprising components that operateasynchronously of one another; an interface element, the interfaceelement having an output and at least two inputs, each input coupled toa respective one of the components, the interface element supplying alogic output signal that is a logic function of signals at the inputs,dependent on the relative timing of the signals at the inputs; a delayelement coupled to cause a relative delay between the times after whichsignals at the inputs affect the interface element; a control circuitfor selectively activating the relative delay caused by the delayelement prior to sampling an output signal of the interface element. 2.An electronic circuit according to claim 1 comprising a test signalsource coupled to the interface element; the control circuit being atest control circuit for switching the electronic circuit between anormal operating mode and the test mode, so that the signals at theinputs become affected by test signals from the test signal sourceduring the test mode, the test control circuit activating said relativedelay in the test mode and keeping the relative delay deactivated in thenormal operating mode.
 3. An electronic circuit according to claim 1,wherein the interface element has enabling inputs, each for enablingsignals from a respective one of the inputs, the control circuit havingan activation output for supplying a deactivation signal followed by anactivation signal during operation, the activation output being coupledto the enabling inputs, at least one of the enabling inputs via thedelay element, so that the delay element causes a difference between thetime intervals after which an activation signal from the activationoutput reaches different ones of the enabling inputs.
 4. An electroniccircuit according to claim 3, wherein the interface element comprises apair of cross-coupled logic gates, at least one of the logic gatescomprising a logic section and power supply interruption elements inseries between an output of the at least one of the logic gates andpower supply connections of the electronic circuit, the power supplyinterruption elements being arranged for switchably interruptingconnections between an output of the at least one of the logic gates andboth power supply connections of the electronic circuit, each input ofthe interface element being coupled to the logic section of a respectiveone of the logic gates, one of the disabling inputs being coupled tocontrol inputs of the power supply connection element of the at leastone of the logic gates.
 5. An electronic circuit according to claim 4,comprising a test control circuit for switching the electronic circuitbetween a normal operating mode and the test mode, the test controlcircuit activating said relative delay in the test mode and deactivatingthe relative delay in the normal operating mode, a scan chain forshifting test patterns in and/or out of the electronic circuit, the testpatterns affecting input signals of the interface element in the testmode, wherein an output node of the at least one of the logic gates isincorporated as a dynamic storage node in the scan chain.
 6. Anelectronic circuit according to claim 2, comprising a scan chain fortransporting test result patterns in the test mode, the scan chain beingcoupled to the interface element for reading information that depends onthe output signal of the interface element.
 7. A method of testing anelectronic circuit that comprises components that operate asynchronouslyof one another and an interface element, the interface element having anoutput and at least two inputs, each input coupled to a respective oneof the components, the interface element supplying a logic output signalthat is a logic function of signals at the inputs and dependent on therelative timing of the signals at the inputs, the method comprisingswitching the electronic circuit to a test mode; applying test inputsignals to the electronic circuit from a test signal source; causing adifference between the time intervals after which the test signal sourceaffects different ones of the signals at the inputs, the test controlcircuit activating said difference in the test mode and keeping thedifference deactivated in the normal operating mode.